1. Field of the Invention
This invention relates generally to differential comparator circuits and more particularly to CMOS differential comparators utilizing hysteresis.
2. Description of the Prior Art
In general, differential comparator circuits exhibit oscillation and noise generation when the output changes from a low-to-high level and from a high-to-low level in response to an input signal slowly crossing the switchpoint voltage of the input devices of the comparator. For TTL comparators, this oscillation occurs at approximately the switchpoint voltage of 1.4 volts. Many such prior art circuits have hysteresis which is the quality of switching from a first state to a second state in response to the magnitude of the input signal crossing one switchpoint and switching from the second state to the first state in response to the magnitude of the input signal crossing a different switchpoint. As noted in Applications of Linear Integrated Circuits by Eugene R. Hnatek (John Wiley & Sons, 1975, pages 251-255 and 278-279) hysteresis is obtainable by using an external resistor to couple a predetermined portion of the positive output voltage back to the non-inverting input of an operational amplifier which is configured as a comparator. However, the minimum amount of hysteresis obtainable is limited by the forward gain and output swing of the comparator which is not small enough for many applications. Furthermore, large external resistors are needed to provide a small amount of hysteresis. Other disadvantages with the prior art include the difficulty of implementing the hysteresis circuits in integrated circuit form in a small area and the dependence of the hysteresis voltage on process variations.